The present invention relates to dynamic random access memory (DRAM) cells and, in particular, to a novel process for their formation.
A dynamic random access memory cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device, such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the electrode (or storage node) area and the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, will generally mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing of storage cells must increase, yet each will maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Recently, attempts to increase the packing density of cell capacitors and/or to simultaneously reduce the transistor size have been made but with limited results. For example, one approach is reducing the length of a transistor gate electrode formed atop a substrate and a source/drain region, to increase therefore the integration density. Unfortunately, reduction of the threshold voltage and/or the so-called short channel effect such as the punch-through phenomenon are likely to appear. A well-known scaling method is effective to improve the above-mentioned disadvantages. However, this approach increases of the substrate density and requires reduction of the supply voltage, which in turn leads to reduction of the margin concerning the electric noise and fluctuations in the threshold voltage.
Accordingly, there is a need for an improved method of forming MOS semiconductor devices, which permits achieving an increased integration of semiconductor circuitry as well as preventing the occurrence of the short-channel effect.
The present invention provides a method of forming memory devices, such as DRAM access transistors, having recessed gate structures. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to adjacent and elevated silicon nitride structures.
These and other advantages and features of the present invention will be more apparent from the detailed description and the accompanying drawings, which illustrate exemplary embodiments of the invention.